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            <div class="title">USB - USB device register descriptions.</div>
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        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 class="panel-title"> USB Register Index</h3>
            </div>
            <div class="panel-body">
                <table>
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000000:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CFG0" target="_self">CFG0 - USB Configuration 0</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000004:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CFG1" target="_self">CFG1 - USB Configuration 1</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000008:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CFG2" target="_self">CFG2 - USB Configuration 2</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000000C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CFG3" target="_self">CFG3 - USB Configuration 3</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000010:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#IDX0" target="_self">IDX0 - Index 0</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000014:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#IDX1" target="_self">IDX1 - Index 1</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000018:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#IDX2" target="_self">IDX2 - Index 2</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000001C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFOADD" target="_self">FIFOADD - IN and OUT endpoint FIFO Address</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000020:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFO0" target="_self">FIFO0 - FIFO0</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000024:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFO1" target="_self">FIFO1 - FIFO1</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000028:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFO2" target="_self">FIFO2 - FIFO2</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000002C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFO3" target="_self">FIFO3 - FIFO3</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000030:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFO4" target="_self">FIFO4 - FIFO4</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000034:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#FIFO5" target="_self">FIFO5 - FIFO5</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000006C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#HWVERS" target="_self">HWVERS - HWVERS</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000078:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#INFO" target="_self">INFO - INFO and SOFT RESET</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000080:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#TIMEOUT1" target="_self">TIMEOUT1 - Chirp Timeout</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00000084:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#TIMEOUT2" target="_self">TIMEOUT2 - HS Signaling Timeout</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00002000:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#CLKCTRL" target="_self">CLKCTRL - USB clocking control</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00002004:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#SRAMCTRL" target="_self">SRAMCTRL - SRAM Control</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00002014:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#UTMISTICKYSTATUS" target="_self">UTMISTICKYSTATUS - PHY UTMI Sticky Status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00002018:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#OBSCLRSTAT" target="_self">OBSCLRSTAT - Clear the sticky PHY OBS status</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x0000201C:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#DPDMPULLDOWN" target="_self">DPDMPULLDOWN - Pull Down for dp dp and dm pins</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00002020:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BCDETSTATUS" target="_self">BCDETSTATUS - USB Battery Charge Detenction</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00002024:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BCDETCRTL1" target="_self">BCDETCRTL1 - BC detection control register</a>
                        </td>
                    </tr>

                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x00002028:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <a class="el" href="#BCDETCRTL2" target="_self">BCDETCRTL2 - BC detection aux register</a>
                        </td>
                    </tr>

                </table>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CFG0" class="panel-title">CFG0 - USB Configuration 0</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0000</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Function address, power management, interrupt status register for EP0 and IN Endpoints 1 to 5</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="10">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">EP5InIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP4InIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP3InIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP2InIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP1InIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP0InIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">ISOUpdate
                                <br>0x0</td>

                            <td align="center" colspan="1">AMSPECIFIC
                                <br>0x0</td>

                            <td align="center" colspan="1">HSEnab
                                <br>0x0</td>

                            <td align="center" colspan="1">HSMode
                                <br>0x0</td>

                            <td align="center" colspan="1">Reset
                                <br>0x0</td>

                            <td align="center" colspan="1">Resume
                                <br>0x0</td>

                            <td align="center" colspan="1">Suspen
                                <br>0x0</td>

                            <td align="center" colspan="1">Enabl
                                <br>0x0</td>

                            <td align="center" colspan="1">Update
                                <br>0x0</td>

                            <td align="center" colspan="7">FuncAddr
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:22</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>EP5InIntStat</td>
                            <td>RO</td>
                            <td>IN Endpoint 5 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>EP4InIntStat</td>
                            <td>RO</td>
                            <td>IN Endpoint 4 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>EP3InIntStat</td>
                            <td>RO</td>
                            <td>IN Endpoint 3 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>EP2InIntStat</td>
                            <td>RO</td>
                            <td>IN Endpoint 2 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>EP1InIntStat</td>
                            <td>RO</td>
                            <td>IN Endpoint 1 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>EP0InIntStat</td>
                            <td>RO</td>
                            <td>IN Endpoint 0 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>ISOUpdate</td>
                            <td>RW</td>
                            <td>Isochronous Transfer Update. When set by the CPU, the USB Controller will wait for an SOF token from the time InPktRdy is set before sending the packet. If an IN token is received before an SOF token, then a zero length data packet will be sent. Note: This bit only affects endpoints performing Isochronous transfers. The ISOUpdate bit affects all IN Isochronous endpoints in the USB Controller. It is normally used as a method of ensuring 'clean' start-up of an IN Isochronous pipe.<br><br>
                                 DONT_WAIT            = 0x0 - Clear for USB Controller not to wait for SOF token before sending packet.<br>
                             WAIT                 = 0x1 - Set to have USB Controller wait for SOF token before sending packet.</td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>AMSPECIFIC</td>
                            <td>RW</td>
                            <td>Software-enabled Connection (SoftConn). When set to 1, the PHY is placed in its normal mode and the D+/D- lines of the USB bus are enabled. When bit is cleared, the PHY is put into non-driving mode and D+ and D- are tri-stated.<br><br>
                                 NOT_CONNECTED        = 0x0 - Clear to disable/disconnect USB lines.<br>
                             CONNECTED            = 0x1 - Set to enable USB lines.</td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>HSEnab</td>
                            <td>RW</td>
                            <td>High-speed Enable. When set by the CPU, the USB Controller will negotiate for high-speed mode when the device is reset by the hub. If not set, the device will only operate in Full-speed mode. The HSEnab bit can be used to disable high-speed operation. Normally the USB Controller will automatically negotiate for high speed operation, when it is reset, by sending a 'chirp' to the hub. However if this bit is cleared then the USB Controller will not send any 'chirps' to the hub so the function will remain in Full-speed mode, even when connected to a high-speed-capable USB.<br><br>
                                 DIS_HS               = 0x0 - Clear to disable High-speed mode (Full-speed mode only).<br>
                             EN_HS                = 0x1 - Set to enable High-speed mode.</td>
                        </tr>

                        <tr>
                            <td>12</td>
                            <td>HSMode</td>
                            <td>RO</td>
                            <td>This read-only bit is set when the USB Controller has successfully negotiated for High-speed mode. The HSMode bit can be used to determine whether the USB Controller is in High-speed mode or Full-speed mode. It will go high when the function has successfully negotiated for high-speed operation during a USB reset.<br><br>
                                 FS_MODE              = 0x0 - Indicates USB Controller is in Full-speed mode only.<br>
                             HS_MODE              = 0x1 - Indicates USB Controller is in High-speed mode.</td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>Reset</td>
                            <td>RO</td>
                            <td>Reset Status. Cleared when either HS negotiation has completed successfully or after 2.1 ms of reset signaling if HS negotiation fails. The Reset bit can be used to determine when reset signaling is present on the USB. Set when Reset signaling is detected and remains high until the bus reverts to an idle state.<br><br>
                                 NEG_RESET_COMPLETE   = 0x0 - Indicates that HS negotiation has completed successfully, or 2.1 ms of reset signaling has elapsed.<br>
                             RESETTING            = 0x1 - Indicates that Reset signaling is detected and remains high until the bus reverts to an idle state.</td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>Resume</td>
                            <td>RW</td>
                            <td>Resume. Set should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. The Resume bit is used to force the USB Controller to generate Resume signaling on the USB to perform remote wake-up from Suspend mode. Once set high, it should be left high for approximately 10 ms (at least 1 ms and no more than 15 ms), then cleared.<br><br>
                                 END_RESUME           = 0x0 - Cleared automatically 10-15 ms after being manually set.<br>
                             RESUME               = 0x1 - Set to force USB Controller to generate Resume signal on the USB to cause remote wake-up from Suspend mode.</td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>Suspen</td>
                            <td>RO</td>
                            <td>Suspend Status. This read-only bit is set when Suspend mode is entered. It is cleared when the CPU reads the interrupt register, or sets the Resume bit of this register. The Suspen bit is set by the USB Controller when Suspend mode is entered. It will be cleared when the CFG2_Suspend field is read (as a result of receiving a Suspend interrupt). It will also be cleared if Suspend mode is left by setting the Resume bit to initiate a remote wake-up.<br><br>
                                 RESUMED              = 0x0 - Indicates that Suspend Mode exited.<br>
                             SUSPENDED            = 0x1 - Indicates that Suspend Mode entered.</td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>Enabl</td>
                            <td>RW</td>
                            <td>Set by the CPU to enable the SUSPENDM signal. The Enabl bit is set to enable the SUSPENDM signal to put the UTM (and any other hardware which uses the SUSPENDM signal) into Suspend mode. If this bit is not set, Suspend mode will be detected as normal but the SUSPENDM signal will remain high so that the UTM does not go into its low-power mode.<br><br>
                                 DISABLE_SUSPENDM     = 0x0 - Clear to disable SUSPENDM signal - UTM does not go into its low-power mode.<br>
                             ENABLE_SUSPENDM      = 0x1 - Set to enable the SUSPENDM signal to put the UTM (and any other HW which uses the SUSPENDM signal) into Suspend mode.</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>Update</td>
                            <td>RO</td>
                            <td>Function Address Update. Set when FuncAddr is written. Cleared when the new address takes effect (at the end of the current transfer).<br><br>
                                 NEW_ADDR_SET         = 0x0 - Indicates that the new address has taken effect.<br>
                             NEW_ADDR_WRITTEN     = 0x1 - Indicates that a new function address has been written to the FuncAddr field.</td>
                        </tr>

                        <tr>
                            <td>6:0</td>
                            <td>FuncAddr</td>
                            <td>RW</td>
                            <td>The function address. This field should be written with the address value contained in the SET_ADDRESS standard device request, when it is received on Endpoint 0. The new address will not take effect immediately as the host will still be using the old address for the Status stage of the device request. The USB Controller will continue to use the old address for decoding packets until the device request has completed. The status of the device request can be determined by reading the Update bit. When a new address is written to this field, the Update bit will be automatically set. It will remain high until the device request has completed and will be cleared when the new address takes effect Note: While the firmware may write the new address to the FuncAddr field immediately when it is received, it is recommended to leave this operation to the Status phase of the operation in case the host aborts the command.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CFG1" class="panel-title">CFG1 - USB Configuration 1</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0004</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Indicates which of the IN Endpoint 1 - 5 interrupts and the single Endpoint 0 interrupt are currently active. Also indicates which of the interrupts for OUT Endpoint 1 - 5 are currently active. All active interrupts are cleared when this register is read.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="10">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">EP5InIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP4InIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP3InIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP2InIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP1InIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP0InIntEn
                                <br>0x0</td>

                            <td align="center" colspan="10">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">EP5OutIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP4OutIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP3OutIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP2OutIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP1OutIntStat
                                <br>0x0</td>

                            <td align="center" colspan="1">EP0OutIntStat
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:22</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>EP5InIntEn</td>
                            <td>RW</td>
                            <td>IN Endpoint 5 Interrupt Enable<br><br>
                                 DIS                  = 0x0 - IN Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - IN Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>EP4InIntEn</td>
                            <td>RW</td>
                            <td>IN Endpoint 4 Interrupt Enable<br><br>
                                 DIS                  = 0x0 - IN Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - IN Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>EP3InIntEn</td>
                            <td>RW</td>
                            <td>IN Endpoint 3 Interrupt Enable<br><br>
                                 DIS                  = 0x0 - IN Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - IN Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>EP2InIntEn</td>
                            <td>RW</td>
                            <td>IN Endpoint 2 Interrupt Enable<br><br>
                                 DIS                  = 0x0 - IN Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - IN Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>EP1InIntEn</td>
                            <td>RW</td>
                            <td>IN Endpoint 1 Interrupt Enable<br><br>
                                 DIS                  = 0x0 - IN Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - IN Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>EP0InIntEn</td>
                            <td>RW</td>
                            <td>IN Endpoint 0 Interrupt Enable<br><br>
                                 DIS                  = 0x0 - IN Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - IN Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>15:6</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>EP5OutIntStat</td>
                            <td>RO</td>
                            <td>OUT Endpoint 5 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>EP4OutIntStat</td>
                            <td>RO</td>
                            <td>OUT Endpoint 4 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>EP3OutIntStat</td>
                            <td>RO</td>
                            <td>OUT Endpoint 3 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>EP2OutIntStat</td>
                            <td>RO</td>
                            <td>OUT Endpoint 2 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>EP1OutIntStat</td>
                            <td>RO</td>
                            <td>OUT Endpoint 1 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>EP0OutIntStat</td>
                            <td>RO</td>
                            <td>OUT Endpoint 0 interrupt status. All interrupts are cleared when the register is read.<br><br>
                                 INACTIVE             = 0x0 - Interrupt inactive.<br>
                             ACTIVE               = 0x1 - Interrupt active.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CFG2" class="panel-title">CFG2 - USB Configuration 2</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0008</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides interrupt enable and (currently active) status bits for each of the state interrupts, as well as the IN Endpoint and OUT Endpoint nterrupts. All active interrupts are cleared when this register is read. On reset, all IN and OUT Endpoint interrupts, in addition to Endpoint 0, are set to 1 while the remaining bits are set to 0.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SOFE
                                <br>0x0</td>

                            <td align="center" colspan="1">ResetE
                                <br>0x1</td>

                            <td align="center" colspan="1">ResumeE
                                <br>0x1</td>

                            <td align="center" colspan="1">SuspendE
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">SOF
                                <br>0x0</td>

                            <td align="center" colspan="1">Reset
                                <br>0x0</td>

                            <td align="center" colspan="1">Resume
                                <br>0x0</td>

                            <td align="center" colspan="1">Suspend
                                <br>0x0</td>

                            <td align="center" colspan="10">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">EP5OutIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP4OutIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP3OutIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP2OutIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP1OutIntEn
                                <br>0x0</td>

                            <td align="center" colspan="1">EP0OutIntEn
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:28</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>27</td>
                            <td>SOFE</td>
                            <td>RW</td>
                            <td>Start of Frame interrupt enable.<br><br>
                                 DIS                  = 0x0 - SOF interrupt disable.<br>
                             EN                   = 0x1 - SOF interrupt enable.</td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>ResetE</td>
                            <td>RW</td>
                            <td>Reset Detect Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Reset detect interrupt disable.<br>
                             EN                   = 0x1 - Reset detect interrupt enable.</td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>ResumeE</td>
                            <td>RW</td>
                            <td>Resume Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Resume interrupt disable.<br>
                             EN                   = 0x1 - Resume interrupt enable.</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>SuspendE</td>
                            <td>RW</td>
                            <td>Suspend Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Suspend interrupt disable.<br>
                             EN                   = 0x1 - Suspend interrupt enable.</td>
                        </tr>

                        <tr>
                            <td>23:20</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>SOF</td>
                            <td>RO</td>
                            <td>Start of Frame Interrupt Status. Set at the start of frame.<br><br>
                                 SOF_INACTIVE         = 0x0 - SOF interrupt inactive.<br>
                             SOF_ACTIVE           = 0x1 - SOF interrupt active.</td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>Reset</td>
                            <td>RO</td>
                            <td>Reset Detect Interrupt Status. Set when reset signaling is detected on the bus.<br><br>
                                 RESET_INACTIVE       = 0x0 - Reset Detect interrupt inactive.<br>
                             RESET_ACTIVE         = 0x1 - Reset Detect interrupt active.</td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>Resume</td>
                            <td>RO</td>
                            <td>Resume Interrupt Status. Set when resume signaling is detected on the bus while the USB Controller is in Suspend mode.<br><br>
                                 RESUME_INACTIVE      = 0x0 - Resume interrupt inactive.<br>
                             RESUME_ACTIVE        = 0x1 - Resume interrupt active.</td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>Suspend</td>
                            <td>RO</td>
                            <td>Suspend Interrupt Status. Set when suspend signaling is detected on the bus.<br><br>
                                 SUSPEND_INACTIVE     = 0x0 - Suspend interrupt inactive.<br>
                             SUSPEND_ACTIVE       = 0x1 - Suspend interrupt active.</td>
                        </tr>

                        <tr>
                            <td>15:6</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>EP5OutIntEn</td>
                            <td>RW</td>
                            <td>Out Endpoint 5 Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Out Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - Out Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>EP4OutIntEn</td>
                            <td>RW</td>
                            <td>Out Endpoint 4 Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Out Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - Out Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>EP3OutIntEn</td>
                            <td>RW</td>
                            <td>Out Endpoint 3 Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Out Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - Out Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>EP2OutIntEn</td>
                            <td>RW</td>
                            <td>Out Endpoint 2 Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Out Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - Out Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>EP1OutIntEn</td>
                            <td>RW</td>
                            <td>Out Endpoint 1 Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Out Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - Out Endpoint interrupt enabled.</td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>EP0OutIntEn</td>
                            <td>RW</td>
                            <td>Out Endpoint 0 Interrupt Enable.<br><br>
                                 DIS                  = 0x0 - Out Endpoint interrupt disabled.<br>
                             EN                   = 0x1 - Out Endpoint interrupt enabled.</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CFG3" class="panel-title">CFG3 - USB Configuration 3</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B000C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides Test fields to put the USB Controller into one of four test modes described in the USB 2.0 specification.  Only one of the Test fields should be set at any time. (Not used in normal operation.) Also includes an index field that determines which endpoint control,status registers are accessed via the IDXn register fields, and a Frame field that holds the last received frame number.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="2">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">ForceFS
                                <br>0x0</td>

                            <td align="center" colspan="1">ForceHS
                                <br>0x0</td>

                            <td align="center" colspan="1">TestPacket
                                <br>0x0</td>

                            <td align="center" colspan="1">TestK
                                <br>0x0</td>

                            <td align="center" colspan="1">TestJ
                                <br>0x0</td>

                            <td align="center" colspan="1">TestSE0NAK
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="4">ENDPOINT
                                <br>0x0</td>

                            <td align="center" colspan="16">FRMNUM
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:30</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>29</td>
                            <td>ForceFS</td>
                            <td>RW</td>
                            <td>Force Full-speed Mode. The CPU sets this bit to force the USB Controller into Full-speed mode when it receives a USB reset.<br><br>
                                 FS_NOT_FORCED        = 0x0 - Do not force FS mode upon USB reset.<br>
                             FS_FORCED            = 0x1 - Force FS mode upon USB reset.</td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>ForceHS</td>
                            <td>RW</td>
                            <td>Force High-speed Mode. The CPU sets this bit to force the USB Controller into High-speed mode when it receives a USB reset.<br><br>
                                 HS_NOT_FORCED        = 0x0 - Do not force HS mode upon USB reset.<br>
                             HS_FORCED            = 0x1 - Force HS mode upon USB reset.</td>
                        </tr>

                        <tr>
                            <td>27</td>
                            <td>TestPacket</td>
                            <td>RW</td>
                            <td>Test Packet Test Mode. The CPU sets this bit to enter the Test_Packet test mode. In this mode, the USB Controller - in high-speed mode - repetitively transmits on the bus a 53-byte test packet. Note: The 53-byte test packet must be loaded into the Endpoint 0 FIFO before the test mode is entered.<br><br>
                                 STOP_TPTM            = 0x0 - Terminates Test Packet Test Mode.<br>
                             START_TPTM           = 0x1 - Initiates Test Packet Test Mode.</td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>TestK</td>
                            <td>RW</td>
                            <td>Test_K Test Mode. The CPU sets this bit to enter the Test_K test mode. In this mode, the USB Controller - in high-speed mode - transmits a continuous K on the bus.<br><br>
                                 STOP_TESTK           = 0x0 - Terminates Test_K Test Mode.<br>
                             START_TESTK          = 0x1 - Initiates Test_K Test Mode.</td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>TestJ</td>
                            <td>RW</td>
                            <td>Test_J Test Mode. The CPU sets this bit to enter the Test_J test mode. In this mode, the USB Controller - in high-speed mode - transmits a continuous J on the bus.<br><br>
                                 STOP_TESTJ           = 0x0 - Terminates Test_J Test Mode.<br>
                             START_TESTJ          = 0x1 - Initiates Test_J Test Mode.</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>TestSE0NAK</td>
                            <td>RW</td>
                            <td>Test_SE0_NAK Test Mode. The CPU sets this bit to enter the Test_SE0_NAK test mode. In this mode, the USB Controller remains in high-speed mode and responds to any valid IN token with a NAK.<br><br>
                                 STOP_TESTSE0NAK      = 0x0 - Terminates Test_SE0_NAK Test Mode.<br>
                             START_TESTSE0NAK     = 0x1 - Initiates Test_SE0_NAK Test Mode.</td>
                        </tr>

                        <tr>
                            <td>23:20</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19:16</td>
                            <td>ENDPOINT</td>
                            <td>RW</td>
                            <td>Index selected endpoint.<br><br>
                                 ENDPOINT0            = 0x0 - Endpoint 0 selected.<br>
                             ENDPOINT1            = 0x1 - Endpoint 1 selected.<br>
                             ENDPOINT2            = 0x2 - Endpoint 2 selected.<br>
                             ENDPOINT3            = 0x3 - Endpoint 3 selected.<br>
                             ENDPOINT4            = 0x4 - Endpoint 4 selected.<br>
                             ENDPOINT5            = 0x5 - Endpoint 5 selected.<br>
                             RSVD                 = 0x6 - 0xf   RESERVED</td>
                        </tr>

                        <tr>
                            <td>15:0</td>
                            <td>FRMNUM</td>
                            <td>RO</td>
                            <td>Frame Number. Read-only field containing the last received frame number in bits 10:0, 15:11 read 0.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="IDX0" class="panel-title">IDX0 - Index 0</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0010</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides additional control and status for IN transactions through the currently-selected endpoint. (To avoid CMSIS conflicts, the address here includes an additional offset of 0x1000. Access to this register must take this into account.) The value returned when this register is read reflects the status of an endpoint specified by setting the endpoint index in the CFG3_ENDPOINT field. When the endpoint index (CFG3_ENDPOINT) = 0, this field provides status and control of Endpoint 0. Also, the MAXPAYLOAD field defines the maximum amount of data that can be transferred through the selected IN endpoint in a single operation. There is a MAXPAYLOAD for each IN endpoint (except Endpoint 0). Note that the action initiated by setting a field in one of the IDXn registers when the selected endpoint has not been configured is undefined.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="1">AutoSet
                                <br>0x0</td>

                            <td align="center" colspan="1">ISO
                                <br>0x0</td>

                            <td align="center" colspan="1">Mode
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FrcDataTog
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DPktBufDis
                                <br>0x0</td>

                            <td align="center" colspan="1">D0
                                <br>0x0</td>

                            <td align="center" colspan="1">IncompTxServiceSetupEnd
                                <br>0x0</td>

                            <td align="center" colspan="1">ClrDataTogServicedOutPktRdy
                                <br>0x0</td>

                            <td align="center" colspan="1">SentStallSendStall
                                <br>0x0</td>

                            <td align="center" colspan="1">SendStallSetupEnd
                                <br>0x0</td>

                            <td align="center" colspan="1">FlushFIFODataEnd
                                <br>0x0</td>

                            <td align="center" colspan="1">UnderRunSentStall
                                <br>0x0</td>

                            <td align="center" colspan="1">FIFONotEmptyInPktRdy
                                <br>0x0</td>

                            <td align="center" colspan="1">InPktRdyOutPktRdy
                                <br>0x0</td>

                            <td align="center" colspan="5">PKTSPLITOPTION
                                <br>0x0</td>

                            <td align="center" colspan="11">MAXPAYLOAD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31</td>
                            <td>AutoSet</td>
                            <td>RW</td>
                            <td>Automatically Set InPktRdy. When set, the FIFONotEmptyInPktRdy field (for IN Endpoint 0) or InPktRdyOutPktRdy field (for IN Endpoint 1-5) in this register will be automatically set when data of the maximum packet size (set in MAXPAYLOAD field) is loaded into the IN FIFO.<br><br>
                                 NO_AUTOSET           = 0x0 - InPktRdy field is not automatically set when MAXPAYLOAD data size is loaded into the IN FIFO.<br>
                             AUTOSET              = 0x1 - Applicable InPktRdy field is automatically set when MAXPAYLOAD data size is loaded into the IN FIFO. If a packet of less than the maximum packet size is loaded, InPktRdy will have to be set manually. Note: Should not be set for high-bandwidth Isochronous endpoints.</td>
                        </tr>

                        <tr>
                            <td>30</td>
                            <td>ISO</td>
                            <td>RW</td>
                            <td>Isochronous Transfers. The CPU sets this bit to enable the IN endpoint for Isochronous transfers (ISO mode) or for Bulk/Interrupt transfers.<br><br>
                                 BULK_INT             = 0x0 - Clear to enable the IN endpoint for Bulk/Interrupt transfers.<br>
                             ISO                  = 0x1 - Set to enable the IN endpoint for Isochronous transfers.</td>
                        </tr>

                        <tr>
                            <td>29</td>
                            <td>Mode</td>
                            <td>RW</td>
                            <td>OUT/IN Mode. The CPU sets this bit to enable the endpoint direction as IN or OUT. Note: Only valid where the endpoint FIFO is used for both IN and OUT transactions, otherwise ignored.<br><br>
                                 OUT                  = 0x0 - Clear to enable the OUT direction for endpoint.<br>
                             IN                   = 0x1 - Set to enable the IN direction for endpoint.</td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>27</td>
                            <td>FrcDataTog</td>
                            <td>RW</td>
                            <td>Force Data Toggle. The CPU sets this bit to force the endpoint's IN data toggle to switch after each data packet is sent regardless of whether an ACK was received. This can be used by Interrupt IN endpoints that are used to communicate rate feedback for Isochronous endpoints.<br><br>
                                 NO_FORCE_TOGGLE      = 0x0 - Keep cleared to not force data toggle.<br>
                             FORCE_TOGGLE         = 0x1 - Set to force the endpoint's IN data toggle to switch after each data packet is sent.</td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>DPktBufDis</td>
                            <td>RW</td>
                            <td>Double Packet Buffer Disable. This bit is used to control the use of Double Packet Buffering. It is ignored when Dynamic FIFO sizing is enabled. Clearing this bit does NOT necessarily enable Double Packet Buffering but rather allows Double Packet Buffering to be determined by the Endpoint's IDX2_INFIFOSZ setting and MAXPAYLOAD size relationship. Default is enabled.<br><br>
                                 EN_DPB               = 0x0 - Clear to allow Double Packet Buffering.<br>
                             DIS_DPB              = 0x1 - Set to disable Double Packet Buffering regardless of the End Point FIFO size and MAXPAYLOAD size relationship.</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>D0</td>
                            <td>RO</td>
                            <td>Unused, always return 0.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>IncompTxServiceSetupEnd</td>
                            <td>RW</td>
                            <td>Incomplete Transmission / Service Setup End. When CFG3_ENDPOINT = 1 to 5, this bit serves as the IncompTx field. When CFG3_ENDPOINT = 0, this bit serves as the ServiceSetupEnd field.If CFG3_ENDPOINT = 0x1-0x5, then this bit serves as the IncompTx field. If the endpoint is being used for high-bandwidth Isochronous transfers, this bit is set to indicate when a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. The remainder of the current packet is then flushed from the FIFO (but any second packet in the FIFO will remain). Note: In anything other than a high bandwidth Isochronous transfer, this bit will always return 0.<br><br>
                                 NO_PACKET_SPLIT      = 0x0 - Packet has NOT been split into multiple packets for transmission.<br>
                             PACKET_SPLIT         = 0x1 - A large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts.If CFG3_ENDPOINT = 0x0, this bit serves as the ServiceSetupEnd field.<br>
                             CLR_SETUPEND         = 0x1 - Set to clear the SetupEnd bit. This bit is cleared automatically.</td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>ClrDataTogServicedOutPktRdy</td>
                            <td>RW</td>
                            <td>Clear Data Toggle / Serviced OUT Packet Ready. When CFG3_ENDPOINT = 1 to 5, this bit serves as the ClrDataTog field. When CFG3_ENDPOINT = 0, this bit serves as the ServicedOutPktReady field.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the ClrDataTog field. Setting this bit resets the endpoint IN data toggle to 0.If CFG3_ENDPOINT = 0x0, this bit serves as the ServicedOutPktReady field. The CPU writes a 1 to this bit to clear the OutPktRdy bit. This bit is cleared automatically.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>SentStallSendStall</td>
                            <td>RW</td>
                            <td>Sent Stall / Send Stall. When CFG3_ENDPOINT = 1 to 5, this bit serves as the SentStall field. When CFG3_ENDPOINT = 0, this bit serves as the SendStall function.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the SentStall field. It is set when a STALL handshake is transmitted. The FIFO is flushed and the InPktRdy bit is cleared. The CPU should clear this bit.If CFG3_ENDPOINT = 0x0, this bit serves as the SendStall field. The CPU sets this bit to terminate the current transaction. The STALL handshake will be transmitted and then this bit will be cleared automatically. Note: This behavior differs from that of the SendStall bits associated with additional IN/OUT endpoints, which need to be cleared by the CPU.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>SendStallSetupEnd</td>
                            <td>RW</td>
                            <td>When CFG3_ENDPOINT = 1 to 5, this bit serves as the SendStall field. When CFG3_ENDPOINT = 0, this bit serves as the SetupEnd field.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the SendStall field. Setting this bit issues a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition.Note: This bit has no effect when the endpoint is being used for Isochronous transfers.If CFG3_ENDPOINT = 0x0, this bit serves as the SetupEnd field. It is set when a control transaction ends before the DataEnd bit has been set. An interrupt will be generated and the FIFO flushed at this time. The bit is cleared by the CPU writing a 1 to the ServicedSetupEnd bit.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>FlushFIFODataEnd</td>
                            <td>RW</td>
                            <td>When CFG3_ENDPOINT = 1 to 5, this bit serves as the FlushFIFO field. When CFG3_ENDPOINT = 0, this bit serves as the DataEnd bit.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the FlushFIFO field. Setting this bit flushes the next packet to be transmitted from the endpoint IN FIFO. The FIFO pointer is reset and the InPktRdy bit is cleared. May be set simultaneously with InPktRdy to abort the packet that has just been loaded into the FIFO.Note 1: FlushFIFO should only be set when InPktRdy is set (at other times, it may cause data corruption).Note 2: If the FIFO contains two packets, FlushFIFO may need to be set twice to completely clear the FIFO.If CFG3_ENDPOINT = 0x0, this bit serves as the DataEnd bit. Set this bit when (1) setting InPktRdy for the last data packet, (2) clearing OutPktRdy after unloading the last data packet, or (3) setting InPktRdy for a zero length data packet.It is cleared automatically.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>UnderRunSentStall</td>
                            <td>RW</td>
                            <td>Under Run / Sent Stall. When CFG3_ENDPOINT = 1 to 5, this bit serves as the UnderRun field. When CFG3_ENDPOINT = 0, this bit serves as the SentStall field.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the UnderRun field. In ISO mode this bit is set when a zero length data packet is sent after receiving an IN token with the InPktRdy bit not set. In Bulk/Interrupt mode, this bit is set when a NAK is returned in response to an IN token. The CPU should clear this bit.If CFG3_ENDPOINT = 0x0, this bit serves as the SentStall field. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>FIFONotEmptyInPktRdy</td>
                            <td>RW</td>
                            <td>FIFO Not Empty / IN Packet Ready. When CFG3_ENDPOINT = 1 to 5, this bit serves as the FIFONotEmpty field. When CFG3_ENDPOINT = 0, this bit serves as the InPktRdy bit.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the FIFONotEmpty field. It is set when there is at least 1 packet in the IN FIFO.If CFG3_ENDPOINT = 0x0, this bit serves as the InPktRdy bit. Set this bit after loading a data packet into the FIFO. It is cleared automatically when the data packet has been transmitted. An interrupt is generated when this bit is cleared (if enabled).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>InPktRdyOutPktRdy</td>
                            <td>RW</td>
                            <td>IN Packet Ready / OUT Packet Ready. When CFG3_ENDPOINT > 0, this bit serves as the InPktRdy field. When CFG3_ENDPOINT = 0, this bit serves as the OutPkyRdy bit.If CFG3_ENDPOINT = 0x1-0x5, this bit serves as the InPktRdy field. Set this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. If the FIFO is double-buffered, it is also automatically cleared when there is space for a second packet in the FIFO. An interrupt is generate (if enabled) when the bit is cleared.If CFG3_ENDPOINT = 0x0, this bit serves as the OutPkyRdy bit. This bit is set when a data packet has been received. An interrupt is generate when this bit is set (if enabled). The CPU clears this bit by setting the ServicedOutPktRdy bit.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:11</td>
                            <td>PKTSPLITOPTION</td>
                            <td>RW</td>
                            <td>Packet Split Option. When IDX0_ISO = 1, this bit serves as the MAXPAYLOAD multiplier for Isochronous IN transfers. When IDX0_ISO = 0, this bit serves as the MAXPAYLOAD multiplier for Bulk IN transfers.If IDX0_ISO = 0x1, this field sets the multiplier for Isochronous transfers. For Isochronous endpoints operating in High-Speed mode and with the High-bandwidth option enabled, PKTSPLITOPTION may be either 2 or 3 (corresponding to this field's bit 0 set or bit 1 set, respectively, and bits[4:2] are ignored) and it specifies the maximum number of such transactions that can take place in a single microframe. If either bit 0 or bit 1 is non-zero, the USB Controller will automatically split any data packet written to the FIFO into up to 2 or 3 'USB' packets, each containing the specified MAXPAYLOAD (or less). The maximum payload for each transaction is 1024 bytes, so this allows up to 3072 bytes to be transmitted in each microframe. (For Isochronous transfers in full-speed mode or if High-bandwidth is not enabled, bits 0 and 1 are ignored.)If IDX0_ISO = 0x0, this field sets the multiplier for Bulk transfers. The field setting can be up to 31, and the multiplier, m, is (field setting + 1).  The multiplier defines the maximum number of 'USB' packets of the specified MAXPAYLOAD data bytes into which a single data packet placed in the FIFO should be split prior to transfer. The data packet is required to be an exact multiple of the MAXPAYLOAD, which is itself required to be either 8, 16, 32, 64 or (in the case of High Speed transfers) 512 bytes.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10:0</td>
                            <td>MAXPAYLOAD</td>
                            <td>RW</td>
                            <td>Maximum Payload transmitted in a single transaction. The total amount of data represented by MAXPAYLOAD x (PKTSPLITOPTION + 1) must not exceed the FIFO size for the IN endpoint, and should not exceed half the FIFO size if double-buffering is required. Note: The value written here (multiplied by PKTSPLITOPTION + 1 in the case of high-bandwidth Isochronous transfers) must match the value given in the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint (see USB Specification Revision 2.0, Chapter 9). A mismatch could cause unexpected results.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="IDX1" class="panel-title">IDX1 - Index 1</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0014</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides control and status bits for OUT transactions through the currently-selected endpoint. It is reset to 0. The value returned when this register is read reflects the status of an endpoint specified by setting the endpoint index in the CFG3_ENDPOINT field. Also, the MAXPAYLOAD field defines the maximum amount of data that can be transferred through the selected OUT endpoint in a single operation. There is a MAXPAYLOAD for each OUT endpoint (except Endpoint 0). Note that the action initiated by setting a field in one of the IDXn registers when the selected endpoint has not been configured is undefined.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="1">AutoClear
                                <br>0x0</td>

                            <td align="center" colspan="1">ISO
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DisNye
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DPktBufDis
                                <br>0x0</td>

                            <td align="center" colspan="1">IncompRx
                                <br>0x0</td>

                            <td align="center" colspan="1">ClrDataTog
                                <br>0x0</td>

                            <td align="center" colspan="1">SentStall
                                <br>0x0</td>

                            <td align="center" colspan="1">SendStall
                                <br>0x0</td>

                            <td align="center" colspan="1">FlushFIFO
                                <br>0x0</td>

                            <td align="center" colspan="1">DataError
                                <br>0x0</td>

                            <td align="center" colspan="1">OverRun
                                <br>0x0</td>

                            <td align="center" colspan="1">FIFOFull
                                <br>0x0</td>

                            <td align="center" colspan="1">OutPktRdy
                                <br>0x0</td>

                            <td align="center" colspan="5">PKTSPLITOPTION
                                <br>0x0</td>

                            <td align="center" colspan="11">MAXPAYLOAD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31</td>
                            <td>AutoClear</td>
                            <td>RW</td>
                            <td>Automatically Clear OutPktRdy.<br><br>
                                 NO_AUTOCLR           = 0x0 - OutPktRdy field will not be automatically cleared when a packet of MAXPAYLOAD data size is unloaded from the OUT FIFO.<br>
                             AUTOCLR              = 0x1 - OutPktRdy field will be automatically cleared when a packet of MAXPAYLOAD data size is unloaded from the OUT FIFO. When packets of less than the maximum packet size are unloaded, OutPktRdy must be cleared manually. Note: Should not be set for high bandwidth Isochronous endpoints.</td>
                        </tr>

                        <tr>
                            <td>30</td>
                            <td>ISO</td>
                            <td>RW</td>
                            <td>Isochronous Transfers. The CPU sets this bit to enable the OUT endpoint for either Isochronous transfers (ISO mode) or for Bulk/Interrupt transfers.<br><br>
                                 BULK_INT             = 0x0 - Clear to enable the OUT endpoint for Bulk/Interrupt transfers.<br>
                             ISO                  = 0x1 - Set to enable the OUT endpoint for Isochronous transfers.</td>
                        </tr>

                        <tr>
                            <td>29</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28</td>
                            <td>DisNye</td>
                            <td>RW</td>
                            <td>Disable NYET Handshakes / PID Error. For Bulk/Interrupt transactions, this bit disable the sending of NYET handshakes. For Bulk/Interrupt transactions, indicates PID errors.If IDX1_ISO = 0x1, this field is read-only and, when set, indicates a PID error in the received packet for Isochronous transfers.If IDX1_ISO = 0x0, this field disables NYET Handshakes for Bulk/Interrupt transactions. Set this bit to disable the sending of NYET handshakes. When set, all successfully received OUT packets are ACK'd including at the point at which the FIFO becomes full.Note: This bit has an effect only in High-speed mode, when it should be set for all Interrupt endpoints.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>27</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>26</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>25</td>
                            <td>DPktBufDis</td>
                            <td>RW</td>
                            <td>Double Packet Buffer Disable. This bit is used to control the use of Double Packet Buffering. It is ignored when Dynamic FIFO sizing is enabled. Clearing this bit does NOT necessarily enable Double Packet Buffering but rather allows Double Packet Buffering to be determined by the Endpoint's IDX2_OUTFIFOSZ setting and MAXPAYLOAD size relationship. Default is enabled.<br><br>
                                 EN_DPB               = 0x0 - Clear to allow Double Packet Buffering.<br>
                             DIS_DPB              = 0x1 - Set to disable Double Packet Buffering regardless of the End Point FIFO size and MAXPAYLOAD size relationship.</td>
                        </tr>

                        <tr>
                            <td>24</td>
                            <td>IncompRx</td>
                            <td>RO</td>
                            <td>Incomplete Receive. This bit is set in a high-bandwidth Isochronous transfer if the packet in the OUT FIFO is incomplete because parts of the data were not received. It is cleared when OutPktRdy is cleared. Note: In anything other than a high-bandwidth Isochronous transfer, this bit will always return 0.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23</td>
                            <td>ClrDataTog</td>
                            <td>RW</td>
                            <td>Clear Data Toggle. Set this bit to reset the endpoint data toggle to 0.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>22</td>
                            <td>SentStall</td>
                            <td>RW</td>
                            <td>Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>21</td>
                            <td>SendStall</td>
                            <td>RW</td>
                            <td>Send Stall. Issues a STALL handshake to a DATA packet.If IDX1_ISO = 0x1, this bit has no effect when the endpoint is being used for Isochronous transfers.If IDX1_ISO = 0x0, this field enables Stall Handshakes for Bulk/Interrupt transactions. Set this bit to issue a STALL handshake to a DATA packet. Clear this bit to terminate the stall condition.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>20</td>
                            <td>FlushFIFO</td>
                            <td>RW</td>
                            <td>Flush FIFO. Set this bit to flush the next packet to be read from the endpoint OUT FIFO. The FIFO pointer is reset and the OutPktRdy bit is cleared. FlushFIFO should only be used when OutPktRdy is set. At other times, it may cause data to be corrupted. If the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>19</td>
                            <td>DataError</td>
                            <td>RO</td>
                            <td>Data Error. Indicates a CRC error.If IDX1_ISO = 0x1 (ISO mode), this bit is set at the same time that OutPktRdy is set if the data packet has a CRC error. It is cleared when OutPktRdy is cleared.If IDX1_ISO = 0x0 (Bulk mode), this field always returns zero. This field is only valid when the endpoint is operating in ISO mode.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>18</td>
                            <td>OverRun</td>
                            <td>RW</td>
                            <td>Overrun Condition. Indicates an overrun.If IDX1_ISO = 0x1 (ISO mode), this bit is set if an OUT packet arrives while FIFOFull is set, i.e., the OUT packet cannot be loaded into the OUT FIFO. The CPU should clear this bit.If IDX1_ISO = 0x0 (Bulk mode), this field always returns zero. This field is only valid when the endpoint is operating in ISO mode.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>FIFOFull</td>
                            <td>RO</td>
                            <td>FIFO Full. When set, this bit indicates that no more packets can be loaded into the OUT FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>OutPktRdy</td>
                            <td>RW</td>
                            <td>OUT Packet Ready. This bit is set when a data packet has been received. Clear this bit when the packet has been unloaded from the OUT FIFO. An interrupt is generated (if enabled) when the bit is set.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:11</td>
                            <td>PKTSPLITOPTION</td>
                            <td>RW</td>
                            <td>Packet Split Option. When IDX1_ISO = 1, this bit serves as the MAXPAYLOAD multiplier for Isochronous OUT transfers. When IDX1_ISO = 0, this bit serves as the MAXPAYLOAD multiplier for Bulk IN transfers.If IDX1_ISO = 0x1, this field sets the multiplier for Isochronous transfers. For Isochronous endpoints operating in High-Speed mode and with the High-bandwidth option enabled, PKTSPLITOPTION may be either 2 or 3 (corresponding to this field's bit 0 set or bit 1 set, respectively, and bits[4:2] are ignored) and it specifies the maximum number of such transactions that can take place in a single microframe. If either bit 0 or bit 1 is non-zero, the USB Controller will automatically combine the separate USB packets received in any microframe into a single packet within the OUT FIFO. The maximum payload for each transaction is 1024 bytes, so this allows up to 3072 bytes to be received in each microframe. (For Isochronous transfers in full-speed mode or if high-bandwidth is not enabled, bits 0 and 1 are ignored.)If IDX1_ISO = 0x0, this field sets the multiplier for Bulk transfers. The field setting can be up to 31, and the multiplier, m, is (field setting + 1).  The multiplier defines the number of USB packets of the specified payload which are to be combined into a single data packet within the FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10:0</td>
                            <td>MAXPAYLOAD</td>
                            <td>RW</td>
                            <td>Maximum Payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Fullspeed and High-speed operations. The total amount of data represented by MAXPAYLOAD x (PKTSPLITOPTION + 1) must not exceed the FIFO size for the OUT endpoint, and should not exceed half the FIFO size if double-buffering is required. Note: The value written here (multiplied by m in the case of high-bandwidth Isochronous transfers) must match the value given in the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint (see USB Specification Revision 2.0, Chapter 9). A mismatch could cause nexpected results.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="IDX2" class="panel-title">IDX2 - Index 2</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0018</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Contains the outcount value for number of received bytes in the packet in the OUT FIFO, and the configurable IN and OUT Endpoint FIFO size.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="5">OUTFIFOSZ
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="5">INFIFOSZ
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="13">ENDPTOUTCOUNT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28:24</td>
                            <td>OUTFIFOSZ</td>
                            <td>RW</td>
                            <td>OUT FIFO Size. Sets the size of the selected OUT endpoint FIFO. Bit 4 of this field defines whether double-packet buffering is supported. When set, double-packet buffering is supported. When cleared, only single-packet buffering is supported. Bits [3:0] of this field determine maximum packet size, where 2^^(b3:b0 + 3) is the maximum packet size to be allowed (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>23:21</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>20:16</td>
                            <td>INFIFOSZ</td>
                            <td>RW</td>
                            <td>IN FIFO Size. Sets the size of the selected IN endpoint FIFO. Bit 4 of this field defines whether double-packet buffering supported. When set, double-packet buffering is supported. When cleared, only single-packet buffering is supported. Bits [3:0] of this field determine maximum packet size, where 2^^(b3:b0 + 3) is the maximum packet size to be allowed (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:13</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12:0</td>
                            <td>ENDPTOUTCOUNT</td>
                            <td>RO</td>
                            <td>Endpoint OUT Count. When CFG3_ENDPOINT = 1 to 5, this read-only field holds the number of received data bytes in the packet in the Endpoint's OUT FIFO. When CFG3_ENDPOINT = 0, this read-only field holds 7-bit data for number of received data bytes in Endpoint 0 FIFO (OUT count). In either case, the value returned changes as the contents of the FIFO change and is only valid while OutPktRdy is set. (IMPORTANT: The address for the OUTCOUNT register is actually the same as COUNT0. However to avoid CMSIS conflicts, the address here includes an additional offset of 0x1000. Access to this register must take this into account.)If CFG3_ENDPOINT = 0x1-0x5, this read-only field holds the number of received data bytes in the packet in the OUT FIFO. If the packet was transmitted as multiple bulk packets, the number given will be for the combined packet.If CFG3_ENDPOINT = 0x0, this read-only field holds 7-bit data for number of received data bytes in Endpoint 0 FIFO (OUT count).<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFOADD" class="panel-title">FIFOADD - IN and OUT endpoint FIFO Address</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B001C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Sets the start address of the selected IN and OUT endpoint FIFOs.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="13">OUTFIFOADD
                                <br>0x0</td>

                            <td align="center" colspan="3">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="13">INFIFOADD
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:29</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>28:16</td>
                            <td>OUTFIFOADD</td>
                            <td>RW</td>
                            <td>Sets the start address of the selected OUT endpoint FIFO.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:13</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12:0</td>
                            <td>INFIFOADD</td>
                            <td>RW</td>
                            <td>Sets the start address of the selected IN endpoint FIFO.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFO0" class="panel-title">FIFO0 - FIFO0</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0020</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Endpoint 0 FIFO register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFO</td>
                            <td>RW</td>
                            <td>Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 0.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFO1" class="panel-title">FIFO1 - FIFO1</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0024</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Endpoint 1 FIFO register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFO</td>
                            <td>RW</td>
                            <td>Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 1.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFO2" class="panel-title">FIFO2 - FIFO2</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0028</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Endpoint 2 FIFO register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFO</td>
                            <td>RW</td>
                            <td>Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 2.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFO3" class="panel-title">FIFO3 - FIFO3</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B002C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Endpoint 3 FIFO register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFO</td>
                            <td>RW</td>
                            <td>Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 3.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFO4" class="panel-title">FIFO4 - FIFO4</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0030</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Endpoint 4 FIFO register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFO</td>
                            <td>RW</td>
                            <td>Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 4.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="FIFO5" class="panel-title">FIFO5 - FIFO5</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0034</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Endpoint 5 FIFO register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="32">FIFO
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:0</td>
                            <td>FIFO</td>
                            <td>RW</td>
                            <td>Writing to this register loads data into the IN FIFO and reading from this register unloads data from the OUT FIFO for endpoint 5.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="HWVERS" class="panel-title">HWVERS - HWVERS</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B006C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Read-only register that returns version number (xx.yyy) of the core hardware.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">RC
                                <br>0x0</td>

                            <td align="center" colspan="5">xx
                                <br>0x0</td>

                            <td align="center" colspan="10">yyy
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15</td>
                            <td>RC</td>
                            <td>RW</td>
                            <td>Unused<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14:10</td>
                            <td>xx</td>
                            <td>RO</td>
                            <td>Major Version Number (Range 0 - 31).<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9:0</td>
                            <td>yyy</td>
                            <td>RO</td>
                            <td>Minor Version Number (Range 0 - 999).<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="INFO" class="panel-title">INFO - INFO and SOFT RESET</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0078</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Contains read-only info of the number of IN and OUT endpoints included in the design, width of the RAM, the ability to reset the USB Controller via software, a soft reset bit for the CLK clock domain and a soft reset bit for the XCLK clock domain.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="14">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">RSTXS
                                <br>0x0</td>

                            <td align="center" colspan="1">RSTS
                                <br>0x0</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="4">RamBits
                                <br>0x0</td>

                            <td align="center" colspan="4">OutEndPoints
                                <br>0x0</td>

                            <td align="center" colspan="4">InEndPoints
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:18</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>17</td>
                            <td>RSTXS</td>
                            <td>RW</td>
                            <td>Soft reset for the XCLK domain. will cause the output signal NRSTXO to be asserted low. This bit is self-clearing. For reset to actually occur, the output NRSTXO must be connected to the input NRSTX.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>RSTS</td>
                            <td>RW</td>
                            <td>Soft reset for the CLK domain. cause the output signal NRSTO to be asserted low. This bit is self-clearing. For reset to actually occur, the output NRSTO must be connected to the input NRST.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:12</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11:8</td>
                            <td>RamBits</td>
                            <td>RO</td>
                            <td>Provides the width of the RAM address bus.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:4</td>
                            <td>OutEndPoints</td>
                            <td>RO</td>
                            <td>Provides the number of implemented OUT Endpoints.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:0</td>
                            <td>InEndPoints</td>
                            <td>RO</td>
                            <td>Provides the number of implemented IN Endpoints.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="TIMEOUT1" class="panel-title">TIMEOUT1 - Chirp Timeout</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0080</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Holds the configurable chirp timeout value.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="16">CTUCH
                                <br>0x4074</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:0</td>
                            <td>CTUCH</td>
                            <td>RW</td>
                            <td>Configurable Chirp Timeout timer; default value of 0x4074 corresponds to a delay of 1.1ms (60Mhz clock cycles * 4 * 0x4074).<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="TIMEOUT2" class="panel-title">TIMEOUT2 - HS Signaling Timeout</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B0084</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Holds the configurable delay from the end of High Speed resume signal to enable UTM normal operating mode.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="16">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="16">CTHRSTN
                                <br>0x32</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:16</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:0</td>
                            <td>CTHRSTN</td>
                            <td>RW</td>
                            <td>Configurable delay from the end of High Speed resume signaling to enabling UTM normal operating mode. Default value of 0x32 corresponds to a delay of 3us. This programmed delay is equivalent to the number of 60MHz clock cycles * 4.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="CLKCTRL" class="panel-title">CLKCTRL - USB clocking control</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B2000</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides optional control for turning off the interface clocks to USB Controller and PHY as well as the reference clock to the USB PHY.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="6">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="2">PHYREFCLKSEL
                                <br>0x0</td>

                            <td align="center" colspan="7">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">PHYAPBLCLKDIS
                                <br>0x0</td>

                            <td align="center" colspan="7">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">CTRLAPBCLKDIS
                                <br>0x0</td>

                            <td align="center" colspan="7">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">PHYREFCLKDIS
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:26</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>25:24</td>
                            <td>PHYREFCLKSEL</td>
                            <td>RW</td>
                            <td>USB PHY reference clock select.For Full_Speed Mode, set the reference CLKSEL to use HFRC-based clock.  For High-Speed Mode, set the reference CLKSEL to use HFRC2-based clock.  The HFRC2-based clock is higher power, but meets the low-jitter requirement for High-Speed Mode.<br><br>
                                 HFRC48               = 0x0 - 48 MHz HFRC-based reference clock for Full-Speed Mode<br>
                             HFRC248              = 0x1 - 48 MHz HFRC2-based reference clock for High-Speed Mode<br>
                             HFRC24               = 0x2 - 24 MHz HFRC-based reference clock for Full-Speed Mode<br>
                             RSVD                 = 0x3 - RESERVED.</td>
                        </tr>

                        <tr>
                            <td>23:17</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>16</td>
                            <td>PHYAPBLCLKDIS</td>
                            <td>RW</td>
                            <td>Setting this bit turns off PHY control logic clock.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>15:9</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8</td>
                            <td>CTRLAPBCLKDIS</td>
                            <td>RW</td>
                            <td>Setting this bit turns off the Controller logic clock.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:1</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>PHYREFCLKDIS</td>
                            <td>RW</td>
                            <td>Setting this bit turns off the PHY reference clock.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="SRAMCTRL" class="panel-title">SRAMCTRL - SRAM Control</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B2004</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Provides optional SRAM tuning control.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="17">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">STOV
                                <br>0x0</td>

                            <td align="center" colspan="1">WABL
                                <br>0x0</td>

                            <td align="center" colspan="3">WABLM
                                <br>0x0</td>

                            <td align="center" colspan="1">RAWL
                                <br>0x0</td>

                            <td align="center" colspan="2">RAWLM
                                <br>0x0</td>

                            <td align="center" colspan="2">EMAW
                                <br>0x3</td>

                            <td align="center" colspan="1">EMAS
                                <br>0x1</td>

                            <td align="center" colspan="3">EMA
                                <br>0x7</td>

                            <td align="center" colspan="1">RET1N
                                <br>0x1</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:15</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>14</td>
                            <td>STOV</td>
                            <td>RW</td>
                            <td>SRAM self-timed override<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>13</td>
                            <td>WABL</td>
                            <td>RW</td>
                            <td>SRAM write assist enable<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>12:10</td>
                            <td>WABLM</td>
                            <td>RW</td>
                            <td>SRAM No margin adjustment<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9</td>
                            <td>RAWL</td>
                            <td>RW</td>
                            <td>SRAM Read assist enable<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>8:7</td>
                            <td>RAWLM</td>
                            <td>RW</td>
                            <td>SRAM Adjustment for margin for this read assist scheme<br><br>
                                 INCDLY               = 0x3 - Increased margin adjustment, increased delay for enabling write assist.<br>
                             MBINCDLY             = 0x2 - Minimum boost level with increased delay for enabling write assist.<br>
                             IMNB                 = 0x1 - Increased margin adjustment with more negative boost.<br>
                             MMNB                 = 0x0 - Minimum margin adjustment with lowest negative boost level.</td>
                        </tr>

                        <tr>
                            <td>6:5</td>
                            <td>EMAW</td>
                            <td>RW</td>
                            <td>Extra margin adjustment for write operations<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>EMAS</td>
                            <td>RW</td>
                            <td>Extra margin adjustment sense amplifier pulse<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3:1</td>
                            <td>EMA</td>
                            <td>RW</td>
                            <td>Extra margin adjustment<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>RET1N</td>
                            <td>RW</td>
                            <td>Retention mode 1 enable, active-LOW<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="UTMISTICKYSTATUS" class="panel-title">UTMISTICKYSTATUS - PHY UTMI Sticky Status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B2014</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>This read only register provides the results from the PHY OBS port controlled by reg 0x20[5:4]. IF any bits are set, the bits are sticky. Clear this register using the OBSCLRSTAT register.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="30">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="2">obsportstciky
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:2</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1:0</td>
                            <td>obsportstciky</td>
                            <td>RO</td>
                            <td>These bits are read only status bits from the PHY OBS port<br><br>
                                 OBS3                 = 0x3 - bit 1:HS BIST results, bit 0:FS BIST results<br>
                             OBS2                 = 0x2 - bit 1: ODT calibration state, bit 0: Current calibration state<br>
                             OBS1                 = 0x1 - bit 1: Rx squelch signal, bit 0: Rx datap<br>
                             OBS0                 = 0x0 - bit 1: PLL lock signal, bit 0: Host Disconnect</td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="OBSCLRSTAT" class="panel-title">OBSCLRSTAT - Clear the sticky PHY OBS status</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B2018</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Clears all bits in the sticky obs status register.</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="31">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">CLRSTAT
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:1</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CLRSTAT</td>
                            <td>WO</td>
                            <td>Writing a 1 to this bit clears all bits in the UTMISTICKYSTATUS register.<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="DPDMPULLDOWN" class="panel-title">DPDMPULLDOWN - Pull Down for dp dp and dm pins</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B201C</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Enables a pulldown resistor(15K) on D+ or D-</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="30">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DPPULLDOWN
                                <br>0x0</td>

                            <td align="center" colspan="1">DMPULLDOWN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:2</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>DPPULLDOWN</td>
                            <td>RW</td>
                            <td>Enables a pulldown resistor(15K) on D+<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DMPULLDOWN</td>
                            <td>RW</td>
                            <td>Enables a pulldown resistor(15K) on D-<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BCDETSTATUS" class="panel-title">BCDETSTATUS - USB Battery Charge Detenction</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B2020</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>USB Battery Charge Detenction Registers</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="26">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">DMCOMPOUT
                                <br>0x0</td>

                            <td align="center" colspan="1">DPCOMPOUT
                                <br>0x0</td>

                            <td align="center" colspan="1">RESERVED03
                                <br>0x0</td>

                            <td align="center" colspan="1">DCPDETECTED
                                <br>0x0</td>

                            <td align="center" colspan="1">CPDETECTED
                                <br>0x0</td>

                            <td align="center" colspan="1">DPATTACHED
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:6</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RESERVED<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>DMCOMPOUT</td>
                            <td>RO</td>
                            <td>DM comparator output<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>DPCOMPOUT</td>
                            <td>RO</td>
                            <td>DP comparator output<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>RESERVED03</td>
                            <td>RO</td>
                            <td>Reserved<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>DCPDETECTED</td>
                            <td>RO</td>
                            <td>Dedicated charging port detected<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>CPDETECTED</td>
                            <td>RO</td>
                            <td>Charging port detected<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>DPATTACHED</td>
                            <td>RO</td>
                            <td>Data pin attachment detected<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BCDETCRTL1" class="panel-title">BCDETCRTL1 - BC detection control register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B2024</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Battery Charging detection main control register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="1">USBSWRESET
                                <br>0x0</td>

                            <td align="center" colspan="19">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">USBDCOMPEN
                                <br>0x0</td>

                            <td align="center" colspan="1">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="2">USBDCOMPREF
                                <br>0x0</td>

                            <td align="center" colspan="1">IDPSINKEN
                                <br>0x0</td>

                            <td align="center" colspan="1">VDMSRCEN
                                <br>0x0</td>

                            <td align="center" colspan="1">RDMPDWNEN
                                <br>0x0</td>

                            <td align="center" colspan="1">VDPSRCEN
                                <br>0x0</td>

                            <td align="center" colspan="1">IDPSRCEN
                                <br>0x0</td>

                            <td align="center" colspan="1">IDMSINKEN
                                <br>0x0</td>

                            <td align="center" colspan="1">BCWEAKPULLDOWNEN
                                <br>0x1</td>

                            <td align="center" colspan="1">BCWEAKPULLUPEN
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31</td>
                            <td>USBSWRESET</td>
                            <td>RW</td>
                            <td>Holds a USB controller and PHY in the reset for BC detection<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>30:12</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RSVD<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11</td>
                            <td>USBDCOMPEN</td>
                            <td>RW</td>
                            <td>Enables DP/DM vendor-specific detection comparator<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>10</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RSVD<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9:8</td>
                            <td>USBDCOMPREF</td>
                            <td>RW</td>
                            <td>Sets DP/DM vendor-specific comparator ref voltage<br><br>
                                 1P25V                = 0x3 - 1.25V<br>
                             2P35                 = 0x2 - 2.35V<br>
                             3P10V                = 0x1 - 3.10V<br>
                             1P65                 = 0x0 - 1.65V (VCCIO/2)</td>
                        </tr>

                        <tr>
                            <td>7</td>
                            <td>IDPSINKEN</td>
                            <td>RW</td>
                            <td>Enables DP current sink<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>6</td>
                            <td>VDMSRCEN</td>
                            <td>RW</td>
                            <td>Enables DM voltage source<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>5</td>
                            <td>RDMPDWNEN</td>
                            <td>RW</td>
                            <td>Enables DM BC 1.2 pull-down resistor<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>4</td>
                            <td>VDPSRCEN</td>
                            <td>RW</td>
                            <td>Enables DP voltage source<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>IDPSRCEN</td>
                            <td>RW</td>
                            <td>Enables DP current source<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>IDMSINKEN</td>
                            <td>RW</td>
                            <td>Enables DM current sink<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>BCWEAKPULLDOWNEN</td>
                            <td>RW</td>
                            <td>Enables weak sink current on DP and DM<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>BCWEAKPULLUPEN</td>
                            <td>RW</td>
                            <td>Enables weak source current to DP and DM<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

        <div class="panel panel-default">
            <div class="panel-heading">
                <h3 id="BCDETCRTL2" class="panel-title">BCDETCRTL2 - BC detection aux register</h3>
            </div>
            <div class="panel-body">
                <h3>Address:</h3>
                <table style="margin:10px">
                    <tr id="row_0_0_">
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">Instance 0 Address:</span>
                        </td>
                        <td class="entry">
                            <span style="width:32px;display:inline-block;">&#160;</span>
                            <span class="h5">0x400B2028</span>
                        </td>
                    </tr>

                </table>
                <h3>Description:</h3>
                <p>Battery Charging auxillary detection control register</p>
                <h3>Register Fields:</h3>
                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>31</th>
                            <th>30</th>
                            <th>29</th>
                            <th>28</th>
                            <th>27</th>
                            <th>26</th>
                            <th>25</th>
                            <th>24</th>
                            <th>23</th>
                            <th>22</th>
                            <th>21</th>
                            <th>20</th>
                            <th>19</th>
                            <th>18</th>
                            <th>17</th>
                            <th>16</th>
                            <th>15</th>
                            <th>14</th>
                            <th>13</th>
                            <th>12</th>
                            <th>11</th>
                            <th>10</th>
                            <th>9</th>
                            <th>8</th>
                            <th>7</th>
                            <th>6</th>
                            <th>5</th>
                            <th>4</th>
                            <th>3</th>
                            <th>2</th>
                            <th>1</th>
                            <th>0</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td align="center" colspan="20">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="2">BCWEAKPULLDOWNTUNE
                                <br>0x1</td>

                            <td align="center" colspan="2">BCWEAKPULLUPTUNE
                                <br>0x1</td>

                            <td align="center" colspan="4">RSVD
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEDCPDET
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCECPDET
                                <br>0x0</td>

                            <td align="center" colspan="1">FORCEDPATTACHED
                                <br>0x0</td>

                            <td align="center" colspan="1">CHARGEDETBYP
                                <br>0x0</td>

                        </tr>
                    </tbody>
                </table>
                <br>

                <table style="margin:10px" class="table table-bordered table-condensed">
                    <thead>
                        <tr>
                            <th>Bits</th>
                            <th>Name</th>
                            <th>RW</th>
                            <th>Description</th>
                        </tr>
                    </thead>
                    <tbody>
                        <tr>
                            <td>31:12</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RSVD<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>11:10</td>
                            <td>BCWEAKPULLDOWNTUNE</td>
                            <td>RW</td>
                            <td>Weak sink resistor to both DP and DM tuning. Trimmable.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>9:8</td>
                            <td>BCWEAKPULLUPTUNE</td>
                            <td>RW</td>
                            <td>Weak source resistor to both DP and DM tuning. Trimmable.<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>7:4</td>
                            <td>RSVD</td>
                            <td>RO</td>
                            <td>RSVD<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>3</td>
                            <td>FORCEDCPDET</td>
                            <td>RW</td>
                            <td>Force output dedicated charging port detected<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>2</td>
                            <td>FORCECPDET</td>
                            <td>RW</td>
                            <td>Force output charging port detected<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>FORCEDPATTACHED</td>
                            <td>RW</td>
                            <td>Force output dp_attached<br><br>
                                </td>
                        </tr>

                        <tr>
                            <td>0</td>
                            <td>CHARGEDETBYP</td>
                            <td>RW</td>
                            <td>BC detection bypass<br><br>
                                </td>
                        </tr>

                    </tbody>
                </table>
                <br>
            </div>
        </div>

    </body>

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            <small>
                AmbiqSuite Register Documentation&nbsp;
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                <img class="footer" src="../resources/ambiqmicro_logo.png" alt="Ambiq Micro"/></a>&nbsp&nbsp Copyright &copy; 2024&nbsp&nbsp<br />
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